The present invention relates to a controller provided on a circuit board along with memory modules so as to control the memory modules, each memory module comprising a source synchronous DRAM which, like a synchronous DRAM, outputs a strobe signal in synchronism with read data and transfers the read data. More particularly, the present invention relates to a data receiver incorporated in the controller and capable of performing high-speed, reliable synchronous data transfer with reference to the memory module.
In general, a semiconductor memory is used as a DIMM (Dual Inline Memory Module) when it is incorporated in a personal computer, etc. Eight or sixteen memory chips are provided on the board of the DIMM, and data or signals are input or output by way of connector pins printed on both sides of the board. A memory board employed in a personal computer or the like has four sockets and a controller, and four DIMMs can be provided on the memory board.
FIG. 1 is a conceptual illustration of a memory board on which a controller 151 and four DIMMs (DIMM1 to DIMM4) are provided. In order to control the memory chips of the DIMMs in synchronism with one another, four clocks CLK are sent from the controller 151 to the four DIMMs in parallel. From the DIMMs, 64-bit parallel data are simultaneously transferred by way of a common data bus.
What becomes a problem with this type of memory board is the timing at which the controller fetches data supplied from each DIMM. Since the distance between the controller and one DIMM differs from that between the controller and another DIMM, the flight time (the time needed for a signal to propagate from one point to another, one point corresponds to the controller, and the second point corresponds to a DIMM) of clock signals and data inevitably differs, depending upon the DIMMs. In other words, the data fetch timing has to be controlled by detecting which DIMM is accessed by the controller.
In order to solve the problems described above, 4-bit strobe signals QS are output in parallel from the DIMMs and supplied to the controller. In the example shown in FIG. 1, the transfer lines through which data DQ and strobe signals QS are sent are under the same load condition, and a 1-bit strobe signal QS is used for each 16-bit data DQ. The controller monitors the strobe signals QS so as to fetch data in synchronism with the receipt of the strobe signals QS.
FIG. 2 shows how clock signal CLK, data, and strobe signal QS are related to one another when the data transfer is executed according to a so-called DDR (Double Date Rate) system, i.e., a system in which 2-bit data are output in response to the rise of clock signal CLK. In FIG. 2, the data transfer from DIMM1 and DIMM4 is also shown, so as to indicate how the signal transmission times are different for the DIMMs. Although DIMM1 and DIMM2 do not simultaneously output data in practice, they are depicted as doing so, so as to indicate the time relationships between them.
When a clock CLK is supplied from the controller to each DIMM, the time needed for the clock CLK to reach DIMM4 is longer than the times needed for the same clock CLK to reach the other DIMMs. Although the memories of the DIMMs output data in synchronism with the clock CLK, the output timings are naturally different. In addition, since the data output from the DIMMs require different lengths of time to reach the controller, the difference between the timings at which the controller receives data inevitably increases. This being so, the controller cannot receive data in synchronism with the clocks CLK; it fetches data, with the strobe signal QS used as a trigger signal. The data window based on which data is fetched in synchronism with the strobe signal QS is restricted due to a so-called skew, i.e., the difference between the timings of data and strobe signals. In FIG. 2, the time indicated by the oblique lines corresponds to the data window. In order to reliably fetch data within a very restricted time range even in a case where the data is supplied to the controller in an asynchronous manner, the data receiver incorporated in the controller to receive data DQ has to be specially designed.